Conference Proceedings

Investigation of circuit-level oxide degradation and its effect on CMOS inverter operation and MOSFET characteristics

BJ Cheek, N Stutzke, S Kumar, RJ Baker, AJ Moll, WB Knowlton

2004 IEEE International Reliability Physics Symposium. Proceedings | Published : 2004

Abstract

Circuit-level oxide degradation effects on CMOS inverter circuit operation and individual MOSFET behavior is investigated. Individual PMOSFET and NMOSFET devices are assembled off-wafer in the inverter configuration through a switch matrix. A range of gate oxide degradation mechanisms are induced by applying a ramped voltage stress (RVS) of various magnitudes to the input of the inverter. A novel circuit model is used to simulate the voltage transfer curves (VTCs) of degraded inverters. At the transistor level, increased gate leakage currents of nearly eight orders of magnitude are observed, in addition to severely reduced on-currents (> 50 percent reduction), and large threshold voltage (Vt..

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