Conference Proceedings
A Low-Power and High-Density Associative Memory in 28 nm CMOS Technology
Alberto Annovi, Giovanni Calderini, Francesco Crescioli, Francesco De Canio, Luca Frontini, Takashi Kubota, Valentino Liberali, Pierluigi Luciano, Fabrizio Palla, Seyed Ruhollah Shojaii, Calliope-Louisa Sotiropoulou, Alberto Stabile, Gianluca Traversi
2017 6TH INTERNATIONAL CONFERENCE ON MODERN CIRCUITS AND SYSTEMS TECHNOLOGIES (MOCAST) | IEEE | Published : 2017
Abstract
In this paper we present a new Associative Memory (AM) chip designed in the 28 nm TSMC HPL technology. Two of the main characteristics of the new chip are reduced power consumption and an increased memory cell area density by the use of two newly designed memory cell technologies. The aim of the new chip is to test the new technologies with realistic front-end functions. The integration of the AM and FPGA is also enhanced. In addition, LVDS drivers and receivers are implemented to strengthen the signal integrity of the I/Os. The new AM chip design is submitted for the fabrication. The die will be packaged in a 17 × 17 Ball Grid Array (BGA) standalone package with a Silicon In Package (SiP) s..
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Awarded by ANR project
Awarded by Australian Research Council - Australian Government
Awarded by EU
Funding Acknowledgements
LPNHE gratefully acknowledges the support from the ANR project ANR-13-BS05-0011. Dr Kubota is the recipient of an Australian Research Council Discovery Early Career Award (DE140100492) funded by the Australian Government. S. Shojaii gratefully acknowledges the support from EU project AIDA-2020 (GA number 654168)