Electronics and firmware of the belle II silicon vertex detector readout system
R Thalmeier, K Adamczyk, H Aihara, C Angelini, T Aziz, V Babu, S Bacher, S Bahinipat, E Barberio, T Baroncelli, AK Basith, G Batgnani, A Bauer, PK Behera, T Bergauer, S Bettarini, B Bhuyan, T Bilka, F Bosi, L Bosisio Show all
Proceedings of Science | Published : 2017
The Silicon Vertex Detector of the Belle II Experiment at KEK in Tsukuba, Japan, consists of 172 double-sided strip sensors. They are read out by 1748 APV25 chips, and the analog data are sent out of the radiation zone to 48 modules which convert them to digital. FPGAs then compensate line signal distortions using digital finite impulse response filters and detect data frames from the incoming stream. Then they perform pedestal subtraction, common mode correction and zero suppression, as well as calculate the peak timing and amplitude of each event from a set of data samples using a neural network.