Conference Proceedings
A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications
A Annovi, A Baschirotto, MM Beretta, NV Biesuz, S Citraro, F Crescioli, M De Matteis, F Fary, L Frontini, P Giannetti, V Liberali, P Luciano, F Palla, A Pezzotta, SR Shojaii, CL Sotiropoulou, A Stabile
Proceedings of the IEEE International Conference on Electronics Circuits and Systems | IEEE | Published : 2016
Abstract
In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks: a 6T SRAM, and a 4T XOR logic gate. Each XORAM cell makes a bitwise comparison between input data and stored data. The memory is organized in 18-bit words, and all the 18 XOR outputs bits must have a low logic value to trigger a high logic value of the single bit match line. A 18-input NOR gate performs this operation. The memory operation is triggered by the change of the least significant bit of the 18-bit input word, which is delayed w.r.t. The other bits. In this way, the logic does not requi..
View full abstract