Characterization of an Associative Memory Chip in 28 nm CMOS Technology
Alberto Annovi, Giovanni Calderini, Stefano Capra, Bruno Checcucci, Francesco Crescioli, Francesco De Canio, Giacomo Fedi, Luca Frontini, Maroua Garci, Christos Gentsos, Takashi Kubota, Valentino Liberali, Fabrizio Palla, Jafar Shojaii, Calliope-Louisa Sotiropoulou, Alberto Stabile, Gianluca Traversi, Sebastien Viret
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | IEEE | Published : 2018
This paper presents the characterization of the new Associative Memory chip (version 7) designed and fabricated in 28 nm CMOS. The design aims at: enhancing links from/to FPGAs; increasing bandwidth thanks to full custom LVDS transceivers; and reducing power consumption and silicon area by means of new memory cells designed with full-custom approach. The design was submitted in December 2016; the prototypes were fabricated and packaged in a 17 × 17 Ball Grid Array (BGA) standalone package. Prototype characterization confirms the chip functionality. The final chip will be assembled in a System In Package (SiP) together with a bare FPGA die.
Related Projects (1)
Awarded by ANR project
Awarded by Australian Government through the Australian Research Council's Discovery Projects funding scheme
Awarded by EU project AIDA-2020
LPNHE gratefully acknowledges the support from the ANR project ANR-13-BS05-0011. The University of Melbourne gratefully acknowledges the support from the Australian Government through the Australian Research Council's Discovery Projects funding scheme (project DP160100315). J. Shojaii gratefully acknowledges the support from EU project AIDA-2020 (GA number 654168).