Adaptive Patterning Design Methodologies

Abstract

Fan-Out Wafer-Level Packaging (FO-WLP) holds immediate promise for packaging semiconductor chips for mobile consumer electronics applications. FO-WLP enables size and performance capabilities similar to Wafer-Level Chip-Scale PAcakging (WLCSP), while extending the capabilities to include multi-device system-in-packages. With lower costs than 2.5D interposer technologies, FO-WLP can support applications that integrate multiple die and devices from heterogenous processes. FO-WLP also provides a path for shrinking die geometries without driving printed circuit boards to smaller interconnects. Industry challenges in handling cost, yield, and the requirement for high die location accuracy after p..