50 GHz static frequency divider in 130 nm CMOS
Y Mo, E Skafidas, R Evans, I Mareels
ELECTRONICS LETTERS | INST ENGINEERING TECHNOLOGY-IET | Published : 2008
A novel circuit topology and design procedure to increase the operating frequency of current model logic (CML) static frequency dividers is proposed. The topology and design procedure are used to design a 50GHz CML static frequency divider in 130nm CMOS. The designed divider has a 20GHz division bandwidth and consumes 11.7mW power from a 1.5V supply. © The Institution of Engineering and Technology 2008.