Conference Proceedings

e-Infrastructure support for nanoCMOS device and circuit simulations

RO Sinnott, G Stewart, A Asenov, C Millar, D Reid, G Roy, S Roy, C Davenhall, B Harbulot, M Jones

Proceedings of the 9th IASTED International Conference on Parallel and Distributed Computing and Networks, PDCN 2010 | Published : 2010


The UK e-Science EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics ( was funded to address the challenges facing the global electronics semiconductor industry caused by the decreasing size of Complementary Metal Oxide Semiconductor (CMOS) transistors and the atomic variability present in devices manifest at these dimensions. Fundamental problems to be addressed include the modelling, understanding and predicting the effect of differences in the atomic structure of devices on their behaviour, and then using this information to guide electronic circuit and system designers who utilise CMOS components. In this paper we describe the e-Infrastru..

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