Journal article
A Framework for Solving Logical Topology Design Problems Within Constrained Computation Time
A Zalesky, HL Vu, M Zukerman, I Ouveysi
IEEE Communications Letters | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | Published : 2003
Abstract
We present a framework for solving logical topology design (LTD) problems in a constrained amount of computation time. Our framework uses a search space dimensionality (SSD) reduction technique that exploits a tradeoff between computation time and solution quality. We have demonstrated that our framework offers improved solution quality in comparison to an existing SSD reduction technique reported in the literature.