Conference Proceedings
A 400-μW 3-GHz comparator in 65-nm CMOS
AT Huynh, B Sedighi, HT Duong, HV Le, E Skafidas
Proceedings of the 2012 IEEE International Symposium on Radio Frequency Integration Technology Rfit 2012 | IEEE | Published : 2012
Abstract
This paper presents a high-speed clocked regenerative comparator designed in 65-nm CMOS process. The kickback noise caused by large variations at the regeneration nodes is suppressed using an intermediate stage. An extra switch is added between regeneration nodes to further equate their voltages when the comparator is at reset phase. The measured results show that the proposed comparator is able to achieve a Bit Error Rate (BER) of 2 × 10 -9 at a sensitivity of 12 mV at 1.4 GHz and 30 mV at 3 GHz. The power consumption of the proposed comparator is 75 μW at 500 MHz and 400 μW at 3 GHz. © 2012 IEEE.
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Funding Acknowledgements
NICTA is funded by the Australian Government as represented by the Department of Broadband, Communications and the Digital Economy and the Australian Research Council through the ICT Centre of Excellence program