Design and implementation of an 11-bit 50-MS/s split SAR ADC in 65 nm CMOS

Abstract

This paper presents the design and implementation of an 11-bit 50-MS/s split successive approximation register (SAR) analog-to-digital converter (ADC) that features a comparator with input-referred offset cancellation, an improved split capacitor digital-to-analog converter (CDAC), and a CDAC mismatch calibrator. In order to reduce the input loading capacitance of the split CDAC, an extra unit capacitor is added to the most significant bit (MSB) array and the input is only sampled onto the bottom plates of the MSB array. Capacitance mismatch between the lowest-bit capacitor of the MSB array and the capacitors of the least significant bit (LSB) array is digitally calibrated. In the design of ..